1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device that performs data allocation.
2. Background Art
Recently, non-volatile semiconductor memory devices are becoming smaller and smaller, and process-induced variations among memory cells depending on the locations thereof are increasing.
In addition, with the advent of multilevel memory cells, which can store multiple-bit information, there is a growing demand for a technique of precisely controlling electrons.
Thus, if data writing is conventionally simply performed in the same procedure, some memory cells require a short time for writing, and other memory cells require a long time for writing.
As a result, an excessively written memory cell or an insufficiently written memory cell, which are referred to as defective bit, can occur. Such a bit causes opposite interpretation of “0” and “1” information.
In order to avoid this, error correction is needed. However, since the error rate varies with location, a simple error correction has a problem that the efficiency of error correction is low.
When recording data, a conventional non-volatile semiconductor memory device divides a data region for a page into a first region and a second region, generates and adds a first error correction code and a second error correction code for the first region and the second region, respectively, and generates and adds a third error correction code for the whole region for the page. When reading the data, syndromes for the first and second regions are determined from the data read from the first and second regions and reproduced data of the first and second error correction codes generated for and added to the first and second regions, the number of errors is determined from the reproduced data read from the whole region for the page and reproduced data of the third error correction code, the error condition of the first and second regions is determined from the first and second syndromes and the number of errors, and an error correction processing is performed. If 1-bit error occurs in each region, 2-bit error data can be corrected (see Japanese Patent Laid-Open Publication No. 2001-202793, for example).
Thus, the conventional technique described above can increase the number of errors that can be corrected without increasing the number of ECC codes.
However, the conventional technique described above does not take into account the fact that the error rate varies with location and does not improve the efficiency of error correction by averaging of the location-dependence error rate.